Video Games Tutorials and News - Ddr5 Is Finally Here. And I've Got It
Intro
In 2014, this stuff came out. Because there's a new kid in town, DDR5. Glasswire, stands out. Keep track of the weird stuff that's connected to your PC even when you aren't using it. With glasswire, it stands out. This is it. My first hands-on with a full retail kit of DD5 memory On the surface, it really doesn't look very different.
In fact, it even has the same 28 pins as DDR4 memory, but don't imagine that you're going to be able to fit it into the same slot. The key has been moved to prevent any but the most determined users from managing to mix up their memory generations. for good reason. One of the biggest changes from DDR4 is immediately visible on our bare board.
Look at this. The power management integrated circuit, or PMI, has been moved from the motherboard to the memory module itself. Now the pmix's role is to take one of the standard output voltages from your computer power supply, in this case, 5 volts, and convert it to the lower 1.1 volts that are required by the ddr5 chips here on the module.
This move was absolutely key to making the signal integrity improvements that were required to ramp DDR5. up to speeds 50 times faster than last gen and even beyond if this alleged leaked roadmap is to be believed. One curious side effect of this, though, is that even though DDr5 runs at nearly 10 percent lower voltages than DDr4, which should lower power draw, the onboard pmic is not going to operate at 100 percent efficiency, meaning that we could actually end up needing to deal with a small amount of waste heat on each module.
G-scale assures me, though, that it's unlikely we'll see a return to those clip-on RAM fans from the DDr2 days. Those things really sucked. They were loud, and the fans failed all the time.
Ddr cash money
Another side effect of moving the PMIC on a module is that it adds cost to the individual modules. So, once you also account for the more complicated PCB design and the early adopter tax, you can expect DDR5 modules to be significantly more expensive than DDR4 modules of the same capacity. In theory, some of this cost should be offset by removing power management from the motherboard, but I've only rarely seen motherboards get cheaper from one generation to the next, and in light of the ongoing worldwide semiconductor shortage, not to mention the inclusion of PCI express gen 5 on these upcoming platforms, which has its own costly trace routing challenges.
I will be pretty surprised if it happens this time.
Advantages over ddr4
The good news, though, is that DD5 comes with some pretty spectacular benefits that aren't immediately obvious on a spec sheet, like I'd forgive you for looking at the launch jdeck DD5 frequency of 4 800 mega transfers per second and thinking.
This sounds pretty unexceptional compared to something like this g-skill kid on the new egg that's rated at a blistering 5300 mega megatransfers per second, especially considering that cast latency, or the number of ram cycles to fulfill a data request, is expected to be in the neighborhood of double compared to last gen, but here's the thing: Remember that article we did recently explaining how frequency alone doesn't paint the full picture of performance? Well, for one thing, the memory controller in your DD4 compatible CPU As with these kinds of speeds in mind, so as with any form of overclocking, it's a bit of a crap shoot whether it'll even work with super fast modules like those ones, and for another, past a certain point, there are actually internal bottlenecks on the memory ics.
Why not just go faster?
That's the chips on the module that would prevent them from properly taking advantage of any additional speed anyway. This part's a little complicated, but bear with me. Internally, each IC has these two-dimensional grids of bits, you know, zeros and ones, and they're called banks. These banks get bundled into bank groups, and to explain it simply, whenever a bank group fires off the data requested by the CPU, that bank group needs a little bit of time to recover.
During that time, the other bank groups fire one after the other to fill up a burst buffer. You can think of it kind of like a minigun, where each barrel is a bank group and the bullets are data bits firing into the buffer. Except, what happens if the module is running at such a high speed that we roll back around to our first bank group before it's recovered?
That's a problem. That could be the bottleneck, so to solve it, DDRR5. This doubles the number of bank groups from four to eight. That gives each bank group way more time to cool down and pretty much guarantees that we'll be able to properly take advantage of speeds well beyond the 6 000 or so mega transfers per second of first generation OC kits like this trident z5. And it gets even more interesting if you're into this sort of thing, which you obviously are because you've made it this far.
Getting around the bottlenecks
The thing is, while the minigun analogy helps us to understand bank group cooldowns, in the real world, it would be terribly inefficient to transfer ones and zeros to the CPU individually, so instead let's imagine that our minigun is shooting all of these bits into an intermediary buffer called the burst buffer, and we can think of this kind of like firing a single shotgun shell full of bits over to the CPU all at once.
This is a bit more impactful right now, ddr4. They are linked to the CPU with a single 64-bit bus or communication channel, and they have a burst length of eight, so we could say that our fully automatic ddr4 shotgun here fires 64 pellet rounds with an eight-round magazine. Bang, bang so 64 bits times eight rounds gives us a total of 64 bytes of data per burst before it needs to be reloaded by our bank groups.
So far so good in DDr5, but modules change this up in a big way. Instead of that single 64-bit bus, we actually have two 32-bit sub-channels that can operate independently. So, back to our shotgun here. We fire smaller shells with only 32 bits each, but we double our burst length or our magazine capacity to 16 per burst. So if we add it up here again, 32 bits times a burst length of 16 is 64 bytes per burst, just like ddr4, except now we've got two barrels that can fire independently, each with its own 16 round magazine.
This isn't dual channel
But don't get carried away. This isn't dual channel and you don't get to just add that total theoretical capacity together to boost your memory bandwidth.
You're still going to want to run multiple DD5 modules in dual channel mode or more channels in the workstation and server space. The real benefit of these independent sub channels is efficiency and latency in DD4. If you only have 32 bits of data in the burst buffer, you just have to fill the rest with junk before you ship it out to the CPU.
